AMD Reveals More R600 Info At 690G Chipset Launch

Various reports hit the net tonight reporting that at today's San Francisco launch of their new 690G chipset AMD decided it was also time to talk a little regarding their recently delayed R600 GPU. Taking advantage of press presence, AMD publicly demoed two R600s coupled to an AMD "Barcelona" CPU and working on a stream computing workload. AMD's Henri Richard took the blame for delaying the R600 launch, but assured everyone that "R600 is doing very well" an obvious bid to quiet rumours of a hardware problem with the GPU being to blame for the launch being pushed back. Further, AMD reported that the launch would only be delayed "by a few weeks" rather than the months some observers have feared. At least one source is reporting directly that the delay is in order that "AMD can roll out a full suite of graphics chips covering multiple market segments for the latest Microsoft DirectX 10 applications programming interface."

In the configuration demoed in San Francisco, each R600 is said to have used 200W, be comprised of 320 "multiply-accumulate units", and between the two units on display be capable of a total of one teraflop of math power. While it's not clear yet which bits are definite AMD marketing language and which are reporters trying to invent language to report with, it would appear to us likely that AMD will also be joining the scalar bandwagon, and that to reach 1 teraflop of compute power with 320 ALUs x 2, would most likely imply a clock of roughly 800MHz operating on MADD units. Going well back to early rumours and reporting of R600 last spring, and adding today's 320 ALUs, this would begin to look like a modified/improved version of Xenos at 4 arrays of 16, with the 5D ALUs improved to be scalar and fully MADD.